P80C557E4EFB/01,55 NXP Semiconductors, P80C557E4EFB/01,55 Datasheet - Page 40

• Manufacturer Part Number: P80C557E4EFB/01,55
• Description: IC 80C51 MCU 1024 ROMLESS 80QFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C557E4EFB/01,55

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 935263156557; P80C557E4FB; P80C557E4FB

Philips Semiconductors
Table 36. Description of IP1 bits
Table 37. Interrupt Priority Structure
Table 38. Interrupt Vector Addresses
1999 Mar 02
External interrupt 0
SIO1 (I
ADC completion
Timer 0 overflow
Timer 2 capture 0
Timer 2 compare 0
External interrupt 1/Seconds interrupt
Timer 2 capture 1
Timer 2 compare 1
Timer 1 overflow
Timer 2 capture 2
Timer 2 compare 2
SIO0 (UART)
Timer 2 capture 3
Timer 2 overflow
External interrupt 0
Timer 0 overflow
External interrupt 1/Seconds interrupt
Timer 1 overflow
SIO0 (UART)
SIO1 (I
Timer 2 capture 0
Timer 2 capture 1
Timer 2 capture 2
Timer 2 capture 3
ADC completion
Timer 2 compare 0
Timer 2 compare 1
Timer 2 compare 2
Timer 2 overflow
Single-chip 8-bit microcontroller
SYMBOL
PCM2
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
PT2
IP1 (F8H)
2
2
C)
C)
IP1.7
IP1.6
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
BIT
SOURCE
SOURCE
PT2
T2 overflow interrupt(s) priority level
T2 comparator 2 interrupt priority level
T2 comparator 1 interrupt priority level
T2 comparator 0 interrupt priority level
T2 capture register 3 interrupt priority level
T2 capture register 2 interrupt priority level
T2 capture register 1 interrupt priority level
T2 capture register 0 interrupt priority level
7
PCM2
6
Figure 38. Interrupt priority register (IP1).
PCM1
5
40
PCM0
4
P83C557E4/P80C557E4/P89C557E4
X1/SEC
X1/SEC
NAME
NAME
ADC
CM0
CM1
CM2
ADC
CM0
CM1
CM2
CT0
CT1
CT2
CT3
CT0
CT1
CT2
CT3
X0
S1
T0
T1
S0
T2
X0
T0
T1
S0
S1
T2
FUNCTION
PCT3
3
PCT2
2
PRIORITY WITHIN LEVEL
VECTOR ADDRESS
PCT1
(highest)
1
(lowest)
000BH
001BH
002BH
003BH
004BH
005BH
006BH
0003H
0013H
0023H
0033H
0043H
0053H
0063H
0073H
Product specification
PCT0
0