ST7FOXK1T6TR STMicroelectronics, ST7FOXK1T6TR Datasheet - Page 112

• Manufacturer Part Number: ST7FOXK1T6TR
• Description: IC MCU 8BIT 4K FLASH 20LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

On-chip peripherals
112/226
Timebase Counter 2
Counter 2 is an 8-bit autoreload upcounter. It can be read by accessing the LTCNTR
register. After an MCU reset, it increments at a frequency of f
stored in the LTARR register. A counter overflow event occurs when the counter rolls over
from FFh to the LTARR reload value. Software can write a new value at any time in the
LTARR register, this value will be automatically loaded in the counter when the next overflow
occurs.
When Counter 2 overflows, the TB2F bit in the LTCSR2 register is set by hardware and an
interrupt request is generated if the TB2IE bit is set. The TB2F bit is cleared by software
reading the LTCSR2 register.
Figure 53. Input Capture timing diagram
Watchdog
When enabled using the WDGE bit, the Watchdog generates a reset after 2 ms (@ = 8 MHz
f
To prevent this watchdog reset occurring, software must set the WDGD bit. The WDGD bit is
cleared by hardware after t
regular intervals to prevent a watchdog reset occurring. Refer to
Note: Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.
A Watchdog reset can be forced at any time by setting the WDGRF bit.
The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the
reset. It is automatically cleared after it has been read.
Hardware Watchdog Option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGE bit in the LTCSR1 is not used.
Refer to the Option byte description.
Using Halt mode with the Watchdog (option)
If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be
used when the watchdog is enabled.
OSC
LTICR REGISTER
8-bit COUNTER 1
).
ICF FLAG
LTIC PIN
f
OSC
f
CPU
/32
01h
(@ 8 MHz f
4µs
WDG
02h
xxh
OSC
. This means that software must write to the WDGD bit at
)
03h
04h
05h
ST7FOXF1, ST7FOXK1, ST7FOXK2
04h
06h
OSC
Figure
/32 starting from the value
07h
54.
LTIC REGISTER
07h
CLEARED
READING
BY S/W
t