ST7FOXK1T6TR STMicroelectronics, ST7FOXK1T6TR Datasheet - Page 92

• Manufacturer Part Number: ST7FOXK1T6TR
• Description: IC MCU 8BIT 4K FLASH 20LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

On-chip peripherals
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Since the Input Capture flags (ICF) for both timers (AT4 timer and LT timer) are set when
signal transition occurs, software must mask one interrupt by clearing the corresponding
ICIE bit before setting the ICS bit.
If the ICS bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the
Input Capture signal because of different values on LTIC and ATIC. To avoid this situation, it
is recommended to do as follows:
1.
2.
3.
4.
Computing a pulse length in long Input Capture mode is not straightforward since both
timers are used. The following steps are required:
1.
2.
Now pulse width P between first capture and second capture is given by:
First, reset both ICIE bits.
Then set the ICS bit.
Reset both ICF bits.
And then set the ICIE bit of desired interrupt.
At the first Input Capture on the rising edge of the pulse, we assume that values in the
registers are the following:
–
–
–
–
At the second Input Capture on the falling edge of the pulse, we assume that the values
in the registers are as follows:
–
–
–
–
where N is the number of overflows of 12-bit CNTR1.
LTICR = LT1
ATICRH = ATH1
ATICRL = ATL1
Hence ATICR1 [11:0] = ATH1 & ATL1. Refer to
LTICR = LT2
ATICRH = ATH2
ATICRL = ATL2
Hence ATICR2 [11:0] = ATH2 & ATL2.
P
+
decimal FFF
=
decimal
(
(
×
(
F9 LT1
×
N
–
)
+
N
+
+
LT2
ATICR2 ATICR1
+
1
)
×
–
ST7FOXF1, ST7FOXK1, ST7FOXK2
0.004ms
Figure 47 on page
–
1
)
×
1ms
93.