ST7FOXK1T6TR STMicroelectronics, ST7FOXK1T6TR Datasheet - Page 66

• Manufacturer Part Number: ST7FOXK1T6TR
• Description: IC MCU 8BIT 4K FLASH 20LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Power saving modes
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Figure 27. Halt timing overview
1. A reset pulse of at least 42 µs must be applied when exiting from Halt mode.
Figure 28. Halt mode flowchart
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
5. The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.
Table 17: ST7FOXF1/ST7FOXK1 Interrupt
during the interrupt routine and cleared when the CC register is popped.
[Active Halt disabled]
INSTRUCTION
RUN
N
HALT INSTRUCTION
(Active Halt disabled)
WATCHDOG
WDGHALT
HALT
RESET
1
INTERRUPT
HALT
Y
1)
mappingfor more details.
256 CPU CYCLE
ENABLE
3)
INTERRUPT
RESET
OR SERVICE INTERRUPT
0
256 CPU CLOCK CYCLE
FETCH RESET VECTOR
DELAY
OR
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BITS
N
DELAY
RESET
Y
WATCHDOG
VECTOR
FETCH
ST7FOXF1, ST7FOXK1, ST7FOXK2
5)
DISABLE
2)
RUN
OFF
OFF
OFF
OFF
ON
ON
X
ON
ON
ON
X
0
4)
4)