Z8F0813HJ005EG Zilog, Z8F0813HJ005EG Datasheet - Page 112

• Manufacturer Part Number: Z8F0813HJ005EG
• Description: IC Z8 ENCORE MCU FLASH 8K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0813HJ005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4182; Z8F0813HJ005EG

PS025203-0405
Note:
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
In MULTIPROCESSOR mode (MPEN = 1), the receive data interrupts are dependent on
the multiprocessor configuration and the most recent address byte.
•
•
•
UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data register. The Break Detect and Overrun status bits are not
displayed until after the valid data has been read.
After the valid data has been read, the UART Status 0 register is updated to indicate the
overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that
the Receive Data register contains a data byte. However, because the overrun error
occurred, this byte may not contain valid data and must be ignored. The BRKD bit indi-
cates if the overrun was caused by a break condition on the line. After reading the status
byte indicating an overrun error, the Receive Data register must be read again to clear the
error bits is the UART Status 0 register. Updates to the Receive Data register occur only
when the next data word is received.
UART Data and Error Handling Procedure
Figure 15 illustrates the recommended procedure for use in UART receiver interrupt ser-
vice routines.
A data byte is received and is available in the UART Receive Data register. This interrupt
can be disabled independently of the other receiver interrupt sources. The received data in-
terrupt occurs after the receive character has been received and placed in the Receive Data
register. To avoid an overrun error, software must respond to this received data available
condition before the next character is completely received.
A break is received
An overrun is detected
A data framing error is detected
P R E L I M I N A R Y
Z8 Encore!
Product Specification
®
Z8F0823 Series
UART
95