Z8F0813HJ005EG Zilog, Z8F0813HJ005EG Datasheet - Page 85

IC Z8 ENCORE MCU FLASH 8K 28SSOP

Z8F0813HJ005EG

Manufacturer Part Number
Z8F0813HJ005EG
Description
IC Z8 ENCORE MCU FLASH 8K 28SSOP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet

Specifications of Z8F0813HJ005EG

Core Processor
Z8
Core Size
8-Bit
Speed
5MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
269-4182
Z8F0813HJ005EG
PS025203-0405
6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
7. Configure the associated GPIO port pin for the Timer Output and Timer Output
8. Write to the Timer Control register to enable the timer and initiate counting.
The PWM period is represented by the following equation:
If an initial starting value other than
registers, the ONE-SHOT mode equation determines the first PWM time-out period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre-
sented by:
PWM Output High Time Ratio (%)
If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre-
sented by:
CAPTURE Mode
In CAPTURE mode, the current timer count value is recorded when the appropriate exter-
nal Timer Input transition occurs. The Capture count value is written to the Timer PWM
High and Low Byte Registers. The timer input is the system clock. The TPOL bit in the
Timer Control register determines if the Capture occurs on a rising edge or a falling edge
of the Timer Input signal. When the Capture event occurs, an interrupt is generated and the
timer continues counting. The INPCAP bit in TxCTL1 register is set to indicate the timer
interrupt is because of an input capture event.
The timer continues counting up to the 16-bit Reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the Reload value, the timer generates an
interrupt and continues counting. The INPCAP bit in TxCTL1 register clears indicating
the timer interrupt is not because of an input capture event.
The steps for configuring a timer for CAPTURE mode and initiating the count are as fol-
lows:
PWM Output High Time Ratio (%)
PWM Period (s)
to the relevant interrupt registers.
Complement alternate functions. The Timer Output Complement function is shared
with the Timer Input function for both timers. Setting the timer mode to Dual PWM
automatically switches the function from Timer In to Timer Out Complement.
=
--------------------------------------------------------------------------- -
System Clock Frequency (Hz)
Reload Value
P R E L I M I N A R Y
0001H
=
=
×
Reload Value PWM Value
----------------------------------------------------------------------- -
Prescale
--------------------------------- -
Reload Value
PWM Value
is loaded into the Timer High and Low Byte
Reload Value
Z8 Encore!
×
100
Product Specification
®
Z8F0823 Series
×
100
Timers
68

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