ST72C254G2M6 STMicroelectronics, ST72C254G2M6 Datasheet - Page 13
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ST72C254G2M6
Manufacturer Part Number
ST72C254G2M6
Description
IC MCU 8BIT 8K FLASH SOIC-28
Manufacturer
STMicroelectronics
Series
ST7r
Datasheets
1.INDART-ST72C254.pdf
(3 pages)
2.ST72C104G1M6.pdf
(141 pages)
3.ST72C215G2M6.pdf
(140 pages)
Specifications of ST72C254G2M6
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3.2 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
ST7
No. Of I/o's
22
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
ST72C2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
3.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDT1-DVP2/US
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72C254G2M6
Manufacturer:
ST
Quantity:
20 000
4 FLASH PROGRAM MEMORY
4.1 INTRODUCTION
FLASH devices have a single voltage non-volatile
FLASH memory that may be programmed in-situ
(or plugged in a programming tool) on a byte-by-
byte basis.
4.2 MAIN FEATURES
■
■
■
■
4.3 STRUCTURAL ORGANISATION
The FLASH program memory is organised in a
single 8-bit wide memory block which can be used
for storing both code and data constants.
The FLASH program memory is mapped in the up-
per part of the ST7 addressing space and includes
the reset and interrupt user vector area .
4.4 IN-SITU PROGRAMMING (ISP) MODE
The FLASH program memory can be programmed
using Remote ISP mode. This ISP mode allows
the contents of the ST7 program memory to be up-
dated using a standard ST7 programming tools af-
ter the device is mounted on the application board.
This feature can be implemented with a minimum
number of added components and board area im-
pact.
An example Remote ISP hardware interface to the
standard ST7 programming tool is described be-
low. For more details on ISP programming, refer to
the ST7 Programming Specification.
Remote ISP Overview
The Remote ISP mode is initiated by a specific se-
quence on the dedicated ISPSEL pin.
The Remote ISP is performed in three steps:
Remote ISP hardware configuration
In Remote ISP mode, the ST7 has to be supplied
with power (V
cillator and application crystal circuit for example).
– Selection of the RAM execution mode
– Download of Remote ISP code in RAM
– Execution of Remote ISP code in RAM to pro-
Remote In-Situ Programming (ISP) mode
Up to 16 bytes programmed in the same cycle
MTP memory (Multiple Time Programmable)
Read-out memory protection against piracy
gram the user program into the FLASH
DD
and V
SS
) and a clock signal (os-
ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
This mode needs five signals (plus the V
if necessary) to be connected to the programming
tool. This signals are:
If any of these pins are used for other purposes on
the application, a serial resistor has to be imple-
mented to avoid a conflict if the other device forces
the signal level.
Figure 5
standard ST7 programming tool. For more details
on the pin locations, refer to the device pinout de-
scription.
Figure 5. Typical Remote ISP Interface
4.5 MEMORY READ-OUT PROTECTION
The read-out protection is enabled through an op-
tion bit.
For FLASH devices, when this option is selected,
the program and data stored in the FLASH memo-
ry are protected against read-out piracy (including
a re-write protection). When this protection option
is removed the entire FLASH program memory is
first automatically erased. However, the E
data memory (when available) can be protected
only with ROM devices.
– RESET: device reset
– V
– ISPCLK: ISP output serial clock pin
– ISPDATA: ISP input serial data pin
– ISPSEL: Remote ISP mode selection. This pin
C
L0
must be connected to V
board through a pull-down resistor.
SS
XTAL
ST7
: device ground power supply
shows a typical hardware interface to a
C
L1
ISPDATA
ISPSEL
ISPCLK
RESET
TO PROGRAMMING TOOL
HE10 CONNECTOR TYPE
V
SS
SS
on the application
10KΩ
APPLICATION
DD
2
47KΩ
PROM
13/141
signal
1