ST72C254G2M6 STMicroelectronics, ST72C254G2M6 Datasheet - Page 77

• Manufacturer Part Number: ST72C254G2M6
• Description: IC MCU 8BIT 8K FLASH SOIC-28
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72C254G2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3.2 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: ST7
• No. Of I/o's: 22
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: ST72C2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MDT1-DVP2/US
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: In Transition

I
Master Transmitter
Following the address transmission and after SR1
register has been read, the master sends bytes
from the DR register to the SDA line via the inter-
nal shift register.
The master waits for a read of the SR1 register fol-
lowed by a write in the DR register, holding the
SCL line low (see
EV8).
When the acknowledge bit is received, the
interface sets:
– EVF and BTF bits with an interrupt if the ITE bit
To close the communication: after writing the last
byte to the DR register, set the STOP bit to gener-
ate the Stop condition. The interface goes auto-
matically back to slave mode (M/SL bit cleared).
Error Cases
– BERR: Detection of a Stop or a Start condition
2
C BUS INTERFACE (Cont’d)
is set.
during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt
if ITE is set.
Note that BERR will not be set if an error is de-
tected during the first pulse of each 9-bit transac-
tion:
Single Master Mode
If a Start or Stop is issued during the first pulse of
a 9-bit transaction, the BERR flag will not be set
and transfer will continue however the BUSY flag
will be reset. To work around this, slave devices
should issue a NACK when they receive a mis-
placed Start or Stop. The reception of a NACK or
BUSY by the master in the middle of communica-
tion gives the possibility to reinitiate transmis-
Figure 3
Transfer sequencing
ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
– AF: Detection of a non-acknowledge bit. In this
– ARLO: Detection of an arbitration lost condition.
Note: In all these cases, the SCL line is not held
low; however,the SDA line can remain low if the
last bits transmitted are all 0. It is then necessary
to release both lines by software. The SCL line is
not held low while AF=1 but by other flags (SB or
BTF) that are set at the same time.
sion.
Multimaster Mode
Normally the BERR bit would be set whenever
unauthorized transmission takes place while
transfer is already in progress. However, an is-
sue will arise if an external master generates an
unauthorized Start or Stop while the I
is on the first pulse pulse of a 9-bit transaction. It
is possible to work around this by polling the
BUSY bit during I
The resetting of the BUSY bit can then be han-
dled in a similar manner as the BERR flag being
set.
case, the EVF and AF bits are set by hardware
with an interrupt if the ITE bit is set. To resume,
set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 reg-
ister. However, if read before the completion of
the transmission, the AF flag will be set again,
thus possibly generating a new interrupt. Soft-
ware must ensure either that the SCL line is back
at 0 before reading the SR2 register, or be able
to correctly handle a second interrupt during the
9th pulse of a transmitted byte.
In this case the ARLO bit is set by hardware (with
an interrupt if the ITE bit is set and the interface
goes automatically back to slave mode (the M/SL
bit is cleared).
2
C master mode transmission.
2
C master
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