ST72C254G2M6 STMicroelectronics, ST72C254G2M6 Datasheet - Page 78
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ST72C254G2M6
Manufacturer Part Number
ST72C254G2M6
Description
IC MCU 8BIT 8K FLASH SOIC-28
Manufacturer
STMicroelectronics
Series
ST7r
Datasheets
1.INDART-ST72C254.pdf
(3 pages)
2.ST72C104G1M6.pdf
(141 pages)
3.ST72C215G2M6.pdf
(140 pages)
Specifications of ST72C254G2M6
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3.2 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
ST7
No. Of I/o's
22
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
ST72C2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
3.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDT1-DVP2/US
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72C254G2M6
Manufacturer:
ST
Quantity:
20 000
ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
I
Figure 45. Transfer Sequencing
Legend: S=Start, S
EVx=Event (with interrupt if ITE=1)
78/141
10-bit Master transmitter
2
7-bit Slave receiver:
S Address
7-bit Slave transmitter:
S Address
7-bit Master receiver:
7-bit Master transmitter:
10-bit Slave receiver:
S Header
10-bit Slave transmitter:
10-bit Master receiver:
S
S
S
C BUS INTERFACE (Cont’d)
EV5
EV5
EV5
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
Address
Address
Header
A
A
A
EV1
EV1 EV3
Address
A
A
A
r
= Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
Data1
EV6
EV6 EV8
EV9
A
Data1
S
Address
S
r
Data1
r
EV1
Header A
EV5
A
Data1
EV2
Data1
A
Header
A
A
Data2
EV3
EV7
EV6 EV8
A
EV1 EV3
A
Data2
EV8
A
Data2
EV2
EV6
A
Data2
Data1
Data1
EV2
A
.....
A
Data1
EV3
EV7
DataN
.....
A
A
A
EV8
EV8
A
EV3
DataN
.....
.....
EV7
A
....
DataN
.....
.....
.
DataN
EV2
DataN
.....
A
DataN
DataN
EV2
P
NA
NA
DataN
A
EV4
P
EV3-1
EV7
EV3-1
A
A
EV4
A
EV8
EV8
P
P
P
EV7
EV4
P
P
EV4
P