ST72C254G2M6 STMicroelectronics, ST72C254G2M6 Datasheet - Page 67
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ST72C254G2M6
Manufacturer Part Number
ST72C254G2M6
Description
IC MCU 8BIT 8K FLASH SOIC-28
Manufacturer
STMicroelectronics
Series
ST7r
Datasheets
1.INDART-ST72C254.pdf
(3 pages)
2.ST72C104G1M6.pdf
(141 pages)
3.ST72C215G2M6.pdf
(140 pages)
Specifications of ST72C254G2M6
Core Processor
ST7
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3.2 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
ST7
No. Of I/o's
22
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
ST72C2x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
3.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7MDT1-DVP2/US
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST72C254G2M6
Manufacturer:
ST
Quantity:
20 000
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.3.4.5 Master Mode Fault
Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.
Master mode fault affects the SPI peripheral in the
following ways:
Clearing the MODF bit is done through a software
sequence:
1. A read or write access to the SR register while
2. A write to the CR register.
Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPE and MSTR bits
– The MODF bit is set and an SPI interrupt is
– The SPE bit is reset. This blocks all output
– The MSTR bit is reset, thus forcing the device
generated if the SPIE bit is set.
from the device and disables the SPI periph-
eral.
into slave mode.
the MODF bit is set.
ST72104Gx, ST72215Gx, ST72216Gx, ST72254Gx
may be restored to their original state during or af-
ter this clearing sequence.
Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.
In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.
The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.
11.3.4.6 Overrun Condition
An overrun condition occurs when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.
In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.
This condition is not detected by the SPI peripher-
al.
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