ST10F276Z5Q3TR STMicroelectronics, ST10F276Z5Q3TR Datasheet - Page 174

• Manufacturer Part Number: ST10F276Z5Q3TR
• Description: MCU 16BIT 832KBIT FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5Q3TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Interface Type: CAN, I2C
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Register set
174/239
Table 85.
XPERCON (F024h / 12h)
Table 86.
GLVL
ILVL
xxIE
xxIR
CAN1EN
CAN2EN
XRAM1EN
XRAM2EN
15
-
-
Bit
Bit
14
-
-
SFR area description
ESFR description
13
-
-
Group level
Defines the internal order for simultaneous requests of the same priority.
’3’: Highest group priority
’0’: Lowest group priority
Interrupt priority level
Defines the priority level for the arbitration of requests.
’Fh’: Highest priority level
’0h’: Lowest priority level
Interrupt enable control bit (individually enables/disables a specific source)
‘0’: Interrupt request is disabled
‘1’: Interrupt request is enabled
Interrupt request flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
CAN1 enable bit
‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled (P4.5
and P4.6 pins can be used as general purpose I/Os, but address range 00’EC00h-
00’EFFFh is directed to external memory only if CAN2EN, XRTCEN, XASCEN,
XSSCEN, XI2CEN, XPWMEN an XMISCEN are ‘0’ also).
‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed.
CAN2 enable bit
‘0’: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled (P4.4
and P4.7 pins can be used as general purpose I/Os, but address range 00’EC00h-
00’EFFFh is directed to external memory only if CAN1EN, XRTCEN, XASCEN,
XSSCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also).
‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed.
XRAM1 enable bit
‘0’: Accesses to the on-chip 2 Kbyte XRAM are disabled. Address range
00’E000h-00’E7FFh is directed to external memory.
‘1’: The on-chip 2 Kbyte XRAM is enabled and can be accessed.
XRAM2 enable bit
‘0’: Accesses to the on-chip 64 Kbyte XRAM are disabled, external access
performed. Address range 0F’0000h-0F’FFFFh is directed to external memory
only if XFLASHEN is ‘0’ also.
‘1’: The on-chip 64 Kbyte XRAM is enabled and can be accessed.
12
-
-
11
-
-
XMISC
RW
10
EN
XI2C
RW
EN
9
ESFR
XSSC
RW
EN
8
XASC
RW
EN
7
Function
Function
XPWM
RW
EN
6
XFLAS
HEN
RW
5
XRTC
RW
EN
4
XRAM2
RW
EN
3
Reset value:- 005h
XRAM1
RW
EN
2
ST10F276Z5
CAN2
RW
EN
1
CAN1
RW
EN
0