ST10F276Z5Q3TR STMicroelectronics, ST10F276Z5Q3TR Datasheet - Page 64

• Manufacturer Part Number: ST10F276Z5Q3TR
• Description: MCU 16BIT 832KBIT FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5Q3TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Interface Type: CAN, I2C
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Bootstrap loader
5.4.6
Note:
Note:
5.4.7
Note:
64/239
Computing the baud rate error
Considering the following conditions, a computation of the error is given as an example.
●
●
In these conditions, the content of PT0 timer for 29 bits should be:
Therefore:
This gives:
Computation of 1 + Tseg1 + Tseg2: Considering the equation:
Thus:
In the algorithm, a rounding up to the superior value is made if the remainder of the division
is greater than half of the divisor. This would have been the case if the PT0 content was 574.
Thus, in this example the result is 1 + Tseg1 + Tseg2 = 10, giving a bit time of exactly 1µs
=> no error in bit rate.
In most cases (24 MHz, 32 MHz, 40 MHz of CPU frequency and 125, 250, 500 or 1Mb/s of
bit rate), there is no error. Nevertheless, it is better to check for an error with the real
application parameters.
The content of the bit timing register is: 0x1640. This gives a sample point at 80%.
The (Re)Synchronization Jump Width is fixed to 2 time quanta.
Bootstrap via CAN
After the bootstrap phase, the ST10F276Z5 CAN module is configured as follows:
●
●
●
No other message is sent by the ST10F276Z5 after the acknowledge.
The CAN boot waits for 128 bytes of data instead of 32 bytes (see UART boot). This is done
to allow the User to reconfigure the CAN bit rate as soon as possible.
CPU frequency: 20 MHz
Target Bit Rate: 1 Mbit/s
The pin P4.6 is configured as output (the latch value is ‘1’ = recessive) to assume
CAN1_TxD function.
The MO2 is configured to output the acknowledge of the bootstrap with the standard
identifier E6h, a DLC of 3 and Data0 = D5h, Data1 and 2 = IDCHIP.
The MO1 is configured to receive messages with the standard identifier 5h. Its
acceptance mask is set to ensure that all bits match. The DLC received is not checked:
The ST10 expects only 1 byte of data at a time.
BRP = 0
tq = 100 ns
[PT0] = 58 x (1 + BRP) x (1 + Tseg1 + Tseg2)
9
[
PT0
=
574
--------- -
58
]
=
≤
29
-------------------------- -
Tseg1
BitRate
574 < [PT0] < 586
×
Fcpu
+
Tseg2
=
29
---------------------------- -
1
×
×
≤
20
10
586
--------- -
58
×
6
6
=
=
10
580
ST10F276Z5