S9S08AW16AE0CFT Freescale Semiconductor, S9S08AW16AE0CFT Datasheet - Page 268

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S9S08AW16AE0CFT

Manufacturer Part Number
S9S08AW16AE0CFT
Description
MCU 16K FLASH AUTO 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of S9S08AW16AE0CFT

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD. POR, PWM, WDT
Number Of I /o
38
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S08AW16AE0CFT
Manufacturer:
FREESCALE
Quantity:
20 000
Chapter 15 Development Support
15.2.3
BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All
commands and data are sent MSB-first using a custom BDC communications protocol. Active background
mode commands require that the target MCU is currently in the active background mode while
non-intrusive commands may be issued at any time whether the target MCU is in active background mode
or running a user application program.
Table 15-1
meaning of each command.
Coding Structure Nomenclature
This nomenclature is used in
268
AAAA
WBKP
WD16
RBKP
RD16
WD
RD
CC
SS
d
/
shows all HCS08 BDC commands, a shorthand description of their coding structure, and the
BDC Commands
=
=
=
=
=
=
=
=
=
=
=
Commands begin with an 8-bit hexadecimal command code in the host-to-target
direction (most significant bit first)
separates parts of the command
delay 16 target BDC clock cycles
a 16-bit address in the host-to-target direction
8 bits of read data in the target-to-host direction
8 bits of write data in the host-to-target direction
16 bits of read data in the target-to-host direction
16 bits of write data in the host-to-target direction
the contents of BDCSCR in the target-to-host direction (STATUS)
8 bits of write data for BDCSCR in the host-to-target direction (CONTROL)
16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint
register)
16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register)
Table 15-1
MC9S08AW60 Data Sheet, Rev 2
to describe the coding structure of the BDC commands.
Freescale Semiconductor

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