S9S08AW16AE0CFT Freescale Semiconductor, S9S08AW16AE0CFT Datasheet - Page 286

• Manufacturer Part Number: S9S08AW16AE0CFT
• Description: MCU 16K FLASH AUTO 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08AW16AE0CFT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD. POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Appendix A Electrical Characteristics and Timing Specifications
Solving equations 1 and 2 for K gives:
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
P
solving equations 1 and 2 iteratively for any value of T
A.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
286
D
(at equilibrium) for a known T
Num C
1
2
3
4
Human Body
Model
Machine Model
Latch-Up
ESD Protection and Latch-Up Immunity
Model
C Human Body Model (HBM)
C Machine Model (MM)
C Charge Device Model (CDM)
C Latch-up Current at T
Series Resistance
Storage Capacitance
Number of Pulse per pin
Series Resistance
Storage Capacitance
Number of Pulse per pin
Minimum input voltage limit
Maximum input voltage limit
Table A-5. ESD and Latch-Up Protection Characteristics
Table A-4. ESD and Latch-up Test Conditions
K = P
A
Rating
A
= 125°C
. Using this value of K, the values of P
D
MC9S08AW60 Data Sheet, Rev 2
× (T
Description
A
+ 273°C) + θ
A
JA
.
× (P
Symbol
V
V
D
V
I
HBM
CDM
LAT
)
MM
2
Symbol
R1
R1
—
—
C
C
± 2000
± 200
± 500
± 100
Min
D
and T
J
Value
1500
–2.5
100
200
can be obtained by
7.5
3
0
3
Freescale Semiconductor
Max
—
—
—
—
Unit
pF
pF
Ω
Ω
V
V
Unit
mA
V
V
V
Eqn. A-3