S9S12P32J0MFT Freescale Semiconductor, S9S12P32J0MFT Datasheet - Page 137

• Manufacturer Part Number: S9S12P32J0MFT
• Description: MCU 128K FLASH AUTO 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12P32J0MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Global Address 0x3_FF06
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR holding register is used to save the condition code
register of the user’s program. It is also used for temporary storage in the standard BDM firmware mode.
The BDM CCR holding register can be written to modify the CCR value.
5.3.2.2
Register Global Address 0x3_FF08
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
Freescale Semiconductor
Special Single-Chip Mode
BPP[3:0]
Reset
BPAE
Field
3–0
7
W
R
All Other Modes
BPAE
BDM Program Page Access Enable Bit — BPAE enables program page access for BDM hardware and
firmware read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD
and WRITE_BD) can not be used for global accesses even if the BGAE bit is set.
0 BDM Program Paging disabled
1 BDM Program Paging enabled
BDM Program Page Index Bits 3–0 — These bits define the selected program page. For more detailed
information regarding the program page window scheme, please refer to the S12S_MMC Block Guide.
BDM Program Page Index Register (BDMPPR)
7
0
When BDM is made active, the CPU stores the content of its CCR register
in the BDMCCR register. However, out of special single-chip reset, the
BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR
register in this CPU mode. Out of reset in all other modes the BDMCCR
register is read zero.
Reset
W
R
= Unimplemented, Reserved
CCR7
6
0
0
Figure 5-5. BDM Program Page Register (BDMPPR)
1
0
7
Figure 5-4. BDM CCR Holding Register (BDMCCR)
Table 5-3. BDMPPR Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
CCR6
1
0
6
5
0
0
CCR5
0
0
5
NOTE
4
0
0
Description
CCR4
0
0
4
BPP3
3
0
CCR3
1
0
3
Background Debug Module (S12SBDMV1)
BPP2
2
0
CCR2
0
0
2
BPP1
1
0
CCR1
1
0
0
BPP0
CCR0
0
0
0
0
0
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