S9S12P32J0MFT Freescale Semiconductor, S9S12P32J0MFT Datasheet - Page 91

• Manufacturer Part Number: S9S12P32J0MFT
• Description: MCU 128K FLASH AUTO 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12P32J0MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
1. Read: Anytime
2.3.46
2.3.47
Freescale Semiconductor
Address 0x025E
Address 0x025F
Write: Anytime
Write: Anytime
Read: Anytime.
Field
7,5-0
PIEP
Field
7,5-0
PIFP
Reset
Reset
W
W
R
R
Port P interrupt enable—
This bit enables or disables on the edge sensitive pin interrupt on the associated pin.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
Port P interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
PIEP7
PIFP7
Port P Interrupt Enable Register (PIEP)
Port P Interrupt Flag Register (PIFP)
0
0
7
7
0
0
0
0
6
6
Figure 2-44. Port P Interrupt Enable Register (PIEP)
Figure 2-45. Port P Interrupt Flag Register (PIFP)
Table 2-41. PIEP Register Field Descriptions
Table 2-42. PIFP Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
PIEP5
PIFP5
5
0
5
0
PIEP4
PIFP4
0
0
4
4
Description
Description
PIEP3
PIFP3
0
0
3
3
PIEP2
PIFP2
0
0
2
2
Port Integration Module (S12PPIMV1)
Access: User read/write
Access: User read/write
PIEP1
PIFP1
0
0
1
1
PIEP0
PIFP0
0
0
0
0
91
(1)
(1)