S9S12P32J0MFT Freescale Semiconductor, S9S12P32J0MFT Datasheet - Page 349

• Manufacturer Part Number: S9S12P32J0MFT
• Description: MCU 128K FLASH AUTO 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12P32J0MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read: anytime
Write: anytime
10.3.2.14 PWM Channel Duty Registers (PWMDTYx)
There is a dedicated duty register for each channel. The value in this register determines the duty of the
associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value
a match occurs and the output changes state.
The duty registers for each channel are double buffered so that if they change while the channel is enabled,
the change will NOT take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform,
not some variation in between. If the channel is not enabled, then writes to the duty register will go directly
to the latches as well as the buffer.
Reference
To calculate the output duty cycle (high time as a % of period) for a particular channel:
Freescale Semiconductor
Module Base + 0x0017
Reset
•
•
•
•
•
W
R
The effective period ends
The counter is written (counter resets to 0x0000)
The channel is disabled
Polarity = 0 (PPOLx = 0)
Polarity = 1 (PPOLx = 1)
Duty cycle = [(PWMPERx PWMDTYx)/PWMPERx] * 100%
Duty cycle = [PWMDTYx / PWMPERx] * 100%
Section 10.4.2.3, “PWM Period and Duty,”
Bit 7
0
7
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active duty due to the double
buffering scheme.
Depending on the polarity bit, the duty registers will contain the count of
either the high time or the low time. If the polarity bit is 1, the output starts
high and then goes low when the duty count is reached, so the duty registers
contain a count of the high time. If the polarity bit is 0, the output starts low
and then goes high when the duty count is reached, so the duty registers
contain a count of the low time.
Figure 10-26. PWM Channel Period Registers (PWMPER5)
6
0
6
S12P-Family Reference Manual, Rev. 1.13
5
0
5
NOTE
NOTE
4
0
4
for more information.
Pulse-Width Modulator (PWM8B6CV1) Block Description
3
0
3
2
0
2
1
0
1
Bit 0
0
0
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