S9S12P32J0MFT Freescale Semiconductor, S9S12P32J0MFT Datasheet - Page 78

• Manufacturer Part Number: S9S12P32J0MFT
• Description: MCU 128K FLASH AUTO 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12P32J0MFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime
1. Read: Anytime
Port Integration Module (S12PPIMV1)
2.3.26
78
Address 0x024A
Write:Never, writes to this register have no effect.
Write: Anytime
DDRS
DDRS
DDRS
Field
Field
PTIS
Reset
3-0
3-2
1
0
W
R
Port S input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Port S data direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port S Data Direction Register (DDRS)
0
0
7
0
0
6
Figure 2-24. Port S Data Direction Register (DDRS)
Table 2-23. DDRS Register Field Descriptions
Table 2-22. PTIS Register Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
5
0
0
0
0
4
Description
Description
DDRS3
0
3
DDRS2
0
2
Access: User read/write
Freescale Semiconductor
DDRS1
0
1
DDRS0
0
0
(1)