MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 156

• Manufacturer Part Number: MC9S12P64CFT
• Description: MCU 16BIT 64K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P64CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12S Debug Module (S12SDBGV2)
6.1.2
The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer
transition. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated.
Independent of comparator matches a transition to Final State with associated tracing and breakpoint can
be triggered immediately by writing to the TRIG control bit.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads. Tracing is disabled when the MCU system is secured.
6.1.3
156
•
•
•
•
•
•
•
Three comparators (A, B and C)
— Comparators A compares the full address bus and full 16-bit data bus
— Comparator A features a data bus mask register
— Comparators B and C compare the full address bus only
— Each comparator features selection of read or write access cycles
— Comparator B allows selection of byte or word access cycles
— Comparator matches can initiate state sequencer transitions
Three comparator modes
— Simple address/data comparator match mode
— Inside address range mode, Addmin ≤ Address ≤ Addmax
— Outside address range match mode, Address < Addmin or Address > Addmax
Two types of matches
— Tagged — This matches just before a specific instruction begins execution
— Force — This is valid on the first instruction boundary after a match occurs
Two types of breakpoints
— CPU breakpoint entering BDM on breakpoint (BDM)
— CPU breakpoint executing SWI on breakpoint (SWI)
Trigger mode independent of comparators
— TRIG Immediate software trigger
Four trace modes
— Normal: change of flow (COF) PC information is stored (see 6.4.5.2.1) for change of flow
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Compressed Pure PC: all program counter addresses are stored
4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin and End alignment of tracing to trigger
definition.
Overview
Features
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor