MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 486

• Manufacturer Part Number: MC9S12P64CFT
• Description: MCU 16BIT 64K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12P64CFT

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S12P
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, DEMO9S12PFAME
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer Module (TIM16B8CV2) Block Description
To operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0
respectively the user must set the corresponding bits IOSx = 1, OMx = 0 and OLx = 0. OC7M7 in the
OC7M register must also be cleared.
14.3.2.9
Read: Anytime
Write: Anytime.
486
Module Base + 0x000A
Module Base + 0x000B
EDGnB
EDGnA
Reset
Reset
Field
7:0
W
W
R
R
EDG7B
EDG3B
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
0
0
7
7
EDG7A
EDG3A
0
0
6
6
EDGnB
Table 14-11. Edge Detector Circuit Configuration
Figure 14-16. Timer Control Register 3 (TCTL3)
Figure 14-17. Timer Control Register 4 (TCTL4)
0
0
1
1
Table 14-10. TCTL3/TCTL4 Field Descriptions
S12P-Family Reference Manual, Rev. 1.13
EDG6B
EDG2B
EDGnA
0
0
5
5
0
1
0
1
EDG6A
EDG2A
Capture on any edge (rising or falling)
0
0
4
4
Capture on falling edges only
Capture on rising edges only
Description
Capture disabled
Configuration
EDG5B
EDG1B
0
0
3
3
EDG5A
EDG1A
0
0
2
2
EDG4B
EDG0B
Freescale Semiconductor
0
0
1
1
EDG4A
EDG0A
0
0
0
0