MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 46
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MC9S12P64CFT
Manufacturer Part Number
MC9S12P64CFT
Description
MCU 16BIT 64K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P64CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1. 16 bits vector address based
Device Overview MC9S12P-Family
1.11.3
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections
for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers.
1.11.3.1
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module section
1.11.3.2
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.11.3.3
Refer to the PIM section for reset configurations of all peripheral module ports.
1.11.3.4
The RAM arrays are not initialized out of reset.
46
Vector Address
Vector base + $AE
Vector base + $8E
Vector base + $8A
Vector base + $90
Vector base + $88
Vector base + $86
Vector base + $84
Vector base + $82
Vector base + $80
Vector base+ $8C
to
Effects of Reset
Flash Configuration Reset Sequence Phase
Reset While Flash Command Active
I/O Pins
Memory
(1)
Autonomous periodical interrupt
PWM emergency shutdown
Low-voltage interrupt (LVI)
High temperature interrupt
ATD compare interrupt
Table 1-12. Interrupt Vector Locations (Sheet 3 of 3)
Spurious interrupt
Interrupt Source
Port P interrupt
(API)
S12P-Family Reference Manual, Rev. 1.13
Mask
CCR
I bit
I bit
I bit
I bit
I bit
I bit
—
Reserved
Reserved
PIEP (PIEP7,PIEP5-PIEP0)
CPMUAPICTRL (APIE)
ATDCTL2 (ACMPIE)
PWMSDN (PWMIE)
CPMUHTCL (HTIE)
CPMUCTRL (LVIE)
Local Enable
None
Freescale Semiconductor
from STOP
Wake up
13.6
Yes
Yes
Yes
No
No
No
-
Initialization.
from WAIT
Wakeup
Yes
Yes
Yes
Yes
Yes
Yes
-
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