MC9S12P64CFT Freescale Semiconductor, MC9S12P64CFT Datasheet - Page 261
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MC9S12P64CFT
Manufacturer Part Number
MC9S12P64CFT
Description
MCU 16BIT 64K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P64CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8.3.2.4
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
1. Read: Anytime
Freescale Semiconductor
Module Base + 0x0003
TSEG2[2:0]
TSEG1[3:0]
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
SAMP
Field
6-4
3-0
7
Reset:
W
R
Sampling — This bit determines the number of CAN bus samples taken per bit time.
0 One sample per bit.
1 Three samples per bit
If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If
SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit
rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
9.
Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
10.
MSCAN Bus Timing Register 1 (CANBTR1)
SAMP
0
7
BRP5
0
0
0
0
1
:
TSEG22
Figure 8-7. MSCAN Bus Timing Register 1 (CANBTR1)
SJW1
BRP4
Table 8-6. Synchronization Jump Width (continued)
0
1
1
0
0
0
0
1
:
0
6
Table 8-8. CANBTR1 Register Field Descriptions
(1)
Figure
Figure
S12P-Family Reference Manual, Rev. 1.13
BRP3
.
0
0
0
0
1
:
TSEG21
Table 8-7. Baud Rate Prescaler
8-44). Time segment 2 (TSEG2) values are programmable as shown in
8-44). Time segment 1 (TSEG1) values are programmable as shown in
0
5
BRP2
0
0
0
0
1
:
TSEG20
SJW0
BRP1
0
4
1
0
1
0
0
1
1
1
:
Description
Freescale’s Scalable Controller Area Network (S12MSCANV3)
BRP0
TSEG13
0
1
0
1
1
:
3
0
Synchronization Jump Width
TSEG12
Prescaler value (P)
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
0
2
64
1
2
3
4
:
Access: User read/write
TSEG11
0
1
TSEG10
Table 8-
Table 8-
0
0
261
(1)
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