MC908GR32AVFAE Freescale Semiconductor, MC908GR32AVFAE Datasheet - Page 224
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MC908GR32AVFAE
Manufacturer Part Number
MC908GR32AVFAE
Description
IC MCU 8BIT 32K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR32AVFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1.5KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR32AVFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Timebase Module (TBM)
16.7 Timebase Control Register
The timebase has one register, the timebase control register (TBCR), which is used to enable the
timebase interrupts and set the rate.
TBIF — Timebase Interrupt Flag
TBR2–TBR0 — Timebase Divider Selection Bits
TACK— Timebase Acknowledge Bit
TBIE — Timebase Interrupt Enabled Bit
TBON — Timebase Enabled Bit
224
This read-only flag bit is set when the timebase counter has rolled over.
These read/write bits select the tap in the counter to be used for timebase interrupts as shown in
Table
The TACK bit is a write-only bit and always reads as 0. Writing a 1 to this bit clears TBIF, the timebase
interrupt flag bit. Writing a 0 to this bit has no effect.
This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the
TBIE bit.
This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption
when its function is not necessary. The counter can be initialized by clearing and then setting this bit.
Reset clears the TBON bit.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
1 = Clear timebase interrupt flag
0 = No effect
1 = Timebase interrupt is enabled.
0 = Timebase interrupt is disabled.
1 = Timebase is enabled.
0 = Timebase is disabled and the counter initialized to 0s.
16-1.
Address: $001C
Do not change TBR2–TBR0 bits while the timebase is enabled (TBON = 1).
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Bit 7
TBIF
0
Figure 16-2. Timebase Control Register (TBCR)
= Unimplemented
TBR2
6
0
TBR1
5
0
NOTE
TBR0
4
0
TACK
3
R
0
0
= Reserved
TBIE
2
0
TBON
1
0
Freescale Semiconductor
Bit 0
R
0
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