MC908GR32AVFAE Freescale Semiconductor, MC908GR32AVFAE Datasheet - Page 34

• Manufacturer Part Number: MC908GR32AVFAE
• Description: IC MCU 8BIT 32K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR32AVFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1.5KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory
34
Addr.
$002C
$002D
$002A
$002B
$002E
$002F
$0024
$0025
$0026
$0027
$0028
$0029
TIM1 Channel 0 Status and
TIM1 Channel 1 Status and
Control Register (T1SC0)
Control Register (T1SC1)
Register High (T2MODH)
Register High (T2CNTH)
Register Low (T1MODL)
Register High (T1CH0H)
Register High (T1CH1H)
TIM2 Status and Control
Register Low (T2MODL)
Register Low (T2CNTL)
Register Low (T1CH0L)
Register Low (T1CH1L)
Register Name
TIM1 Counter Modulo
TIM2 Counter Modulo
TIM2 Counter Modulo
Register (T2SC)
TIM1 Channel 0
TIM1 Channel 0
TIM1 Channel 1
TIM1 Channel 1
See page 236.
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See page 240.
See page 237.
See page 240.
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MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
TIM2 Counter
TIM2 Counter
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 9)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
CH0F
Bit 15
CH1F
Bit 15
Bit 15
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
TOF
Bit 7
Bit 7
1
0
0
0
0
0
0
0
0
1
1
= Unimplemented
CH0IE
CH1IE
TOIE
14
14
14
14
6
6
1
0
6
0
6
0
0
6
0
1
6
1
TSTOP
MS0B
13
13
13
13
5
5
1
0
5
0
0
5
1
0
5
0
1
5
1
R = Reserved
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
MS1A
MS0A
TRST
12
12
12
12
4
4
1
0
4
0
4
0
0
0
4
0
1
4
1
ELS0B
ELS1B
11
11
11
11
3
3
1
0
3
0
3
0
0
0
3
0
1
3
1
U = Unaffected
ELS0A
ELS1A
PS2
10
10
10
10
2
2
1
0
2
0
2
0
0
2
0
1
2
1
Freescale Semiconductor
TOV1
TOV0
PS1
1
1
1
0
9
1
0
9
1
0
9
0
1
0
9
1
1
1
CH0MAX
CH1MAX
Bit 0
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
PS0
1
0
0
0
0
0
1
1