R5F21292SNSP#U0 Renesas Electronics America, R5F21292SNSP#U0 Datasheet - Page 257

• Manufacturer Part Number: R5F21292SNSP#U0
• Description: MCU 3/5V 16K+2K 20PIN-SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/29r

Specifications of R5F21292SNSP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/28 Group, R8C/29 Group
Rev.2.10
REJ09B0279-0210
15.1
Table 15.1
NOTES:
Transfer data format
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
Select functions
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 15.1 lists the Specifications of Clock Synchronous Serial I/O Mode. Table 15.2 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode.
1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the UiC0
2. If an overrun error occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR
register is set to 0 (transmit data output at falling edge and receive data input at rising edge of
transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output
at rising edge and receive data input at falling edge of transfer clock).
bit in the SiRIC register remains unchanged.
Clock Synchronous Serial I/O Mode
Sep 26, 2008
Item
Specifications of Clock Synchronous Serial I/O Mode
Page 238 of 441
• Transfer data length: 8 bits
• CKDIR bit in U0MR register is set to 0 (internal clock): fi/(2(n+1))
• The CKDIR bit is set to 1 (external clock): input from CLK0 pin
• Before transmission starts, the following requirements must be met
• Before reception starts, the following requirements must be met
• When transmitting, one of the following conditions can be selected
• When receiving
• Overrun error
• CLK polarity selection
• LSB first, MSB first selection
• Continuous receive mode selection
fi = f1, f8, f32 n = value set in U0BRG register: 00h to FFh
- The TE bit in the U0C1 register is set to 1 (transmission enabled)
- The TI bit in the U0C1 register is set to 0 (data in the U0TB register)
- The RE bit in the U0C1 register is set to 1 (reception enabled)
- The TE bit in the U0C1 register is set to 1 (transmission enabled)
- The TI bit in the U0C1 register is set to 0 (data in the U0TB register)
- The U0IRS bit is set to 0 (transmit buffer empty):
- The U0IRS bit is set to 1 (transmission completes):
When data transfer from the UART0 receive register to the U0RB register
(when reception completes).
This error occurs if the serial interface starts receiving the next data item
before reading the U0RB register and receives the 7th bit of the next data.
Transfer data input/output can be selected to occur synchronously with
the rising or the falling edge of the transfer clock.
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
Receive is enabled immediately by reading the U0RB register.
When transferring data from the U0TB register to UART0 transmit
register (when transmission starts).
When completing data transmission from UART0 transmit register.
(2)
Specification
15. Serial Interface
(1)
(1)