R5F21292SNSP#U0 Renesas Electronics America, R5F21292SNSP#U0 Datasheet - Page 332
R5F21292SNSP#U0
Manufacturer Part Number
R5F21292SNSP#U0
Description
MCU 3/5V 16K+2K 20PIN-SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/29r
Datasheet
1.R5F21282SNSPU0.pdf
(473 pages)
Specifications of R5F21292SNSP#U0
Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-SSOP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/28 Group, R8C/29 Group
Rev.2.10
REJ09B0279-0210
17. Hardware LIN
The hardware LIN performs LIN communication in cooperation with timer RA and UART0.
17.1
Figure 17.1
RXD0 pin
TXD0 pin
The hardware LIN has the features listed below.
Figure 17.1 shows a Block Diagram of Hardware LIN.
Master mode
Slave mode
• Generates Synch Break
• Detects bus collision
• Detects Synch Break
• Measures Synch Field
• Controls Synch Break and Synch Field signal inputs to UART0
• Detects bus collision
NOTE:
Features
Sep 26, 2008
LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register
TIOSEL: Bit in TRAIOC register
TE: Bit in U0C1 register
1. The WakeUp function is detected by INT1.
LSTART bit
Hardware LIN
Block Diagram of Hardware LIN
LINE bit
SBE bit
Page 313 of 441
RXD0 input
control
circuit
Synch Field
control
circuit
TIOSEL = 0
TIOSEL = 1
Bus collision
detection
circuit
MST bit
and SFIE bits
BCIE, SBIE,
RXD data
Interrupt
control
circuit
Timer RA output pulse
UART0 transfer clock
UART0 TXD data
UART0 TE bit
underflow signal
Timer RA
Timer RA
UART0
17. Hardware LIN
Timer RA
interrupt
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