C8051F343-GQ Silicon Laboratories Inc, C8051F343-GQ Datasheet - Page 142
![IC 8051 MCU FLASH 32K 32LQFP](/photos/12/37/123738/c8051f343-gq_sml.jpg)
C8051F343-GQ
Manufacturer Part Number
C8051F343-GQ
Description
IC 8051 MCU FLASH 32K 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Specifications of C8051F343-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
I2C, SMBus, SPI, UART, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
Package
32LQFP
Device Core
8051
Family Name
C8051F34x
Maximum Speed
48 MHz
Data Rom Size
128 B
A/d Bit Size
10 bit
A/d Channels Available
17
Height
1.4 mm
Length
7 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
7 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1301
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F343-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F343-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
15. Port Input/Output
Digital and analog resources are available through 40 I/O pins (48-pin packages) or 25 I/O pins (32-pin
packages). Port pins are organized as shown in Figure 15.1. Each of the Port pins can be defined as gen-
eral-purpose I/O (GPIO) or analog input; Port pins P0.0-P3.7 can be assigned to one of the internal digital
resources as shown in Figure 15.3. The designer has complete control over which functions are assigned,
limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the
use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corre-
sponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 15.3 and Figure 15.4). The registers XBR0, XBR1, and XBR2 defined in SFR Definition 15.1, SFR
Definition 15.2, and SFR Definition 15.3, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 15.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3,4). Com-
plete Electrical Specifications for Port I/O are given in Table 15.1 on page 158.
142
Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3)
Highest
Priority
Lowest
Priority
SYSCLK
UART1**
Outputs
Outputs
UART0
SMBus
T0, T1
P0
P1
P2
P3
PCA
CP0
CP1
SPI
(P3.0-P3.7*)
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
2
4
2
2
2
6
2
2
8
8
8
8
Rev. 1.3
XBR0, XBR1, XBR2,
PnSKIP Registers
Crossbar
Decoder
Priority
Digital
8
8
8
8
PnMDIN Registers
*P3.1-P3.7 only available on 48-pin
packages
**UART1 only available on
C8051F340/1/4/5/8/A/B devices
PnMDOUT,
Cells
Cells
Cells
Cells
I/O
I/O
I/O
I/O
P0
P1
P2
P3
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7*
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