C8051F343-GQ Silicon Laboratories Inc, C8051F343-GQ Datasheet - Page 190
![IC 8051 MCU FLASH 32K 32LQFP](/photos/12/37/123738/c8051f343-gq_sml.jpg)
C8051F343-GQ
Manufacturer Part Number
C8051F343-GQ
Description
IC 8051 MCU FLASH 32K 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Specifications of C8051F343-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
I2C, SMBus, SPI, UART, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
Package
32LQFP
Device Core
8051
Family Name
C8051F34x
Maximum Speed
48 MHz
Data Rom Size
128 B
A/d Bit Size
10 bit
A/d Channels Available
17
Height
1.4 mm
Length
7 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
7 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1301
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F343-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F343-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
- Current page: 190 of 276
- Download datasheet (2Mb)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 17.3 illustrates a typical
SMBus transaction.
SCL
SDA
SLA6
SLA5-0
R/W
D7
D6-0
START
Slave Address + R/W
ACK
Data Byte
NACK
STOP
Figure 17.3. SMBus Transaction
17.3.1. Arbitration
A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL
and SDA lines remain high for a specified time (see
Section “17.3.4. SCL High (SMBus Free) Timeout”
on page 191
). In the event that two or more devices attempt to begin a transfer at the same time, an arbi-
tration scheme is employed to force one master to give up the bus. The master devices continue transmit-
ting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will
be pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The win-
ning master continues its transmission without interruption; the losing master becomes a slave and
receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device
always wins, and no data is lost.
190
Rev. 1.3
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