C8051F343-GQ Silicon Laboratories Inc, C8051F343-GQ Datasheet - Page 99
![IC 8051 MCU FLASH 32K 32LQFP](/photos/12/37/123738/c8051f343-gq_sml.jpg)
C8051F343-GQ
Manufacturer Part Number
C8051F343-GQ
Description
IC 8051 MCU FLASH 32K 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Specifications of C8051F343-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
I2C, SMBus, SPI, UART, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
Package
32LQFP
Device Core
8051
Family Name
C8051F34x
Maximum Speed
48 MHz
Data Rom Size
128 B
A/d Bit Size
10 bit
A/d Channels Available
17
Height
1.4 mm
Length
7 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
7 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1301
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F343-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F343-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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10. Prefetch Engine
The 48 MHz versions of the C8051F34x family of devices incorporate a 2-byte prefetch engine. Because
the access time of the FLASH memory is 40 ns, and the minimum instruction time is roughly 20 ns, the
prefetch engine is necessary for full-speed code execution. Instructions are read from FLASH memory two
bytes at a time by the prefetch engine, and given to the CIP-51 processor core to execute. When running
linear code (code without any jumps or branches), the prefetch engine allows instructions to be executed
at full speed. When a code branch occurs, the processor may be stalled for up to two clock cycles while the
next set of code bytes is retrieved from FLASH memory. The FLRT bit (FLSCL.4) determines how many
clock cycles are used to read each set of two code bytes from FLASH. When operating from a system
clock of 25 MHz or less, the FLRT bit should be set to ‘0’ so that the prefetch engine takes only one clock
cycle for each read. When operating with a system clock of greater than 25 MHz (up to 48 MHz), the FLRT
bit should be set to ‘1’, so that each prefetch code read lasts for two clock cycles.
Bits 7–6: Unused. Read = 00b; Write = Don’t Care
Bit 5:
Bits 4–1: Unused. Read = 0000b; Write = Don’t Care
Bit 0:
Bit7
R
PFEN: Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
FLBWE: FLASH Block Write Enable.
This bit allows block writes to FLASH memory from software.
0: Each byte of a software FLASH write is written individually.
1: FLASH bytes are written in groups of two.
Bit6
SFR Definition 10.1. PFE0CN: Prefetch Engine Control
R
PFEN
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bit4
R
Rev. 1.3
Bit3
R
Bit2
R
Bit1
R
SFR Address: 0xAF
FLBWE
R/W
Bit0
00100000
Reset Value
99
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