R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 110

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 10.12
FMR0 Register
(flash memory
(flash memory
FMSTP Bit
operates)
stops)
When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register
and the CM07 bit in the CM0 register, as described in Figure 10.12.
The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock
when the WAIT instruction is executed.
Figure 10.12 shows the Time from Wait Mode to Interrupt Routine Execution.
Wait mode
0
1
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting wait mode.
Feb 29, 2008
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function
interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).
Time from Wait Mode to Interrupt Routine Execution
(system clock)
(system clock)
CM0 Register
(XCIN clock)
(XCIN clock)
CM07 Bit
0
1
0
1
Interrupt request generated
activation sequence
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Flash memory
× 12 cycles + 30 µs (max.)
× 12 cycles + 30 µs (max.)
Time until Flash Memory
T1
Period of system clock
Period of system clock
Period of XCIN clock
Period of XCIN clock
is Activated (T1)
× 12 cycles
× 12 cycles
CPU clock restart sequence
Time until CPU Clock
Period of CPU clock
is Supplied (T2)
Same as above
Same as above
Same as above
T2
× 6 cycles
Period of CPU clock
Time for Interrupt
Same as above
Same as above
Same as above
Sequence (T3)
× 20 cycles
Interrupt sequence
10. Clock Generation Circuit
T3
Following total
time is the time
from wait mode
until an interrupt
routine is
executed.
Remarks