R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 256

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Table 14.31
i = 0 or 1, j = either A, B, C, or D
NOTE:
Count sources
Count operations
PWM operations
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOB0 pin function
TRDIOD0 pin function
TRDIOA1 pin function
TRDIOC1 pin function
TRDIOB1 pin function
TRDIOD1 pin function
TRDIOC0 pin function
INT0 pin function
Read from timer
Write to timer
Select functions
1. After a count starts, the PWM period is fixed.
Feb 29, 2008
Item
Complementary PWM Mode Specifications
Page 237 of 485
f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a program)
Set bits TCK2 to TCK0 in the TRDCR1 register to the same value (same count
source) as bits TCK2 to TCK0 in the TRDCR0 register.
Increment or decrement
Registers TRD0 and TRD1 are decremented with the compare match in registers
TRD0 and TRDGRA0 during increment operation. The TRD1 register value is
changed from 0000h to FFFFh during decrement operation, and registers TRD0 and
TRD1 are incremented.
PWM period: 1/fk × (m+2-p) × 2
Dead time: p
Active level width of normal-phase: 1/fk × (m-n-p+1) × 2
Active level width of counter-phase: 1/fk × (n+1-p) × 2
1 (count starts) is written to bits TSTART0 and TSTART1 in the TRDSTR register.
0 (count stops) is written to bits TSTART0 and TSTART1 in the TRDSTR register
when the CSEL0 bit in the TRDSTR register is set to 1.
(The PWM output pin holds output level before the count stops.)
• Compare match (The content of the TRDi register matches content of the TRDGRji
• The TRD1 register underflows
Programmable I/O port or TRDCLK (external clock) input
PWM1 output normal-phase output
PWM1 output counter-phase output
PWM2 output normal-phase output
PWM2 output counter-phase output
PWM3 output normal-phase output
PWM3 output counter-phase output
Output inverted every 1/2 period of PWM
Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input
The count value can be read by reading the TRDi register.
The value can be written to the TRDi register.
• Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse Output Forced
• The active level of normal-phase and counter-phase and initial output level
• Transfer timing from the buffer register selected
• A/D trigger generated
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRB0 register (PWM1 output)
p: Value set in the TRD0 register
register.)
Cutoff.)
selected individually
Counter-phase
Normal-phase
Value set in the TRDGRA1 register (PWM2 output)
Value set in the TRDGRB1 register (PWM3 output)
n+1-p
n+1
m+2-p
p
(1)
m-p-n+1
Specification
(When “L” is selected as the active level)
14. Timers