R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 394

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 17.7
17.4.2
IR bit in the TRAIC
RXDSF flag in the
SBDCT flag in the
SFDCT flag in the
Figure 17.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure
17.8 through Figure 17.10 show a flowchart for the procedure for receiving a header field.
When receiving a header field, the hardware LIN operates as described below.
LINCR register
RXD0 input for
LINST register
LINST register
(1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware
(2) When “L” level is input for a duration equal to or greater than the period set in timer RA, the hardware
(3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and
(4) The hardware LIN sets the SFDCT flag in the LINST register to 1 when it finishes measuring the Synch
(5) After it finishes measuring the Synch Field, calculate a transfer rate from the count value of timer RA
(6) The hardware LIN performs communication for a response field after it finishes receiving the ID field.
Feb 29, 2008
RXD0 pin
Slave Mode
register
LIN.
LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1.
Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA
interrupt. Then it goes to Synch Field measurement.
bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal
to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly.
Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt.
and set to UART0 and registers TRAPRE and TRA of timer RA again.
UART0
Typical Operation when Receiving a Header Field
1
0
1
0
1
0
1
0
1
0
1
0
The above applies under the following conditions:
LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
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(1)
Set by writing 1 to
the LSTART bit in
the LINCR register
Synch Break
(2)
(3)
Measure this period
Set by writing 1 to
the B1CLR bit in
the LINST register
Cleared to 0 upon
acceptance of
interrupt request or
by a program
Synch Field
(4)
(5)
Set by writing 1 to the
B0CLR bit in the LINST
register
Cleared to 0 when Synch
Field measurement
finishes
IDENTIFIER
17. Hardware LIN
(6)