MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 158

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.67
2.3.68
158
Address 0x026E
Address 0x026F
Write: Anytime.
Write: Anytime.
Read: Anytime.
Field
Field
PIEJ
PIFJ
Reset
Reset
7-0
7-0
W
W
R
R
Port J interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port J.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
Port J interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSJ register. To clear this flag, write logic level 1 to the corresponding bit in the PIFJ register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
PIEJ7
PIFJ7
Port J Interrupt Enable Register (PIEJ)
Port J Interrupt Flag Register (PIFJ)
0
0
7
7
PIEJ6
PIFJ6
0
0
6
6
Figure 2-65. Port J Interrupt Enable Register (PIEJ)
Figure 2-66. Port J Interrupt Flag Register (PIFJ)
Table 2-63. PPSP Register Field Descriptions
Table 2-64. PPSP Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
PIEJ5
PIFJ5
0
0
5
5
PIEJ4
PIFJ4
0
0
4
4
Description
Description
PIEJ3
PIFJ3
3
0
3
0
PIEJ2
PIFJ2
0
0
2
2
Access: User read/write
Access: User read/write
Freescale Semiconductor
PIEJ1
PIFJ1
0
0
1
1
PIEJ0
PIFJ0
0
0
0
0
(1)
(1)