MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 538

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.3.2.2
Read or write: Anytime but reads will always return 0x0000 (1 state is transient).
All bits reset to zero.
14.3.2.3
Read or write: Anytime
All bits reset to zero.
538
Module Base + 0x0001
Module Base + 0x0002
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
FOC[7:0]
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
7:0
W
W
R
R
OC7M7
FOC7
Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note: A channel 7 event, which can be a counter overflow when TTOV[7] is set or A successful channel 7 output
Timer Compare Force Register (CFORC)
Output Compare 7 Mask Register (OC7M)
0
0
0
7
7
compare overrides any channel 6:0 compares. If a forced output compare on any channel occurs at the
same time as the successful output compare, then the forced output compare action will take precedence
and the interrupt flag will not get set.
OC7M6
FOC6
Figure 14-5. Output Compare 7 Mask Register (OC7M)
0
0
0
6
6
Figure 14-4. Timer Compare Force Register (CFORC)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 14-3. CFORC Field Descriptions
OC7M5
FOC5
5
0
0
5
0
OC7M4
FOC4
0
0
0
4
4
Description
OC7M3
FOC3
0
0
0
3
3
OC7M2
FOC2
2
0
0
2
0
OC7M1
Freescale Semiconductor
FOC1
0
0
0
1
1
OC7M0
FOC0
0
0
0
0
0