MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 164

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.78
2.3.79
164
DDR0AD1
Function
Address 0x0279
Address 0x027A
PT1AD1
Write: Anytime.
Write: Anytime.
Altern.
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
DDR0AD17
PT1AD17
Port AD1 general purpose input/output data—Data Register
This register is associated with ATD1 analog inputs AN[7:0] on PAD[23:16], respectively.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port AD1 data direction—
This register controls the data direction of pins 15 through 8.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port AD1 Data Register 1 (PT1AD1)
Port AD1 Data Direction Register 0 (DDR0AD1)
AN7
0
0
7
7
DDR0AD16
PT1AD16
Figure 2-77. Port AD1 Data Direction Register 0 (DDR0AD1)
AN6
0
0
6
6
Table 2-75. DDR0AD1 Register Field Descriptions
Figure 2-76. Port AD1 Data Register 1 (PT1AD1)
Table 2-74. PT1AD1 Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
DDR0AD15
PT1AD15
AN5
0
0
5
5
DDR0AD14
PT1AD14
AN4
0
0
4
4
Description
Description
DDR0AD13
PT1AD13
AN3
3
0
3
0
DDR0AD12
PT1AD12
AN2
0
0
2
2
DDR0AD11
PT1AD11
Access: User read/write
Access: User read/write
Freescale Semiconductor
AN1
0
0
1
1
DDR0AD10
PT1AD10
AN0
0
0
0
0
(1)
(1)