MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 232

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Memory Protection Unit (S12XMPUV1)
access is allowed or represents an access violation. If an access violation caused by the S12X CPU is
detected, the MPU module raises an access violation interrupt. If the MPU module detects an access
violation caused by a bus master other than the S12X CPU, it flags an access error condition to the
respective master. In addition to the restrictions defined for memory ranges in the MPU descriptors,
accesses to memory not covered by any MPU descriptor (even read accesses!) are considered access
violations.
Figure 4-1
4.1.3
1. Master 3 can be implemented or left out depending the chip configuration. Please refer to the Device Reference Manual for
information about the availability and function of Master 3.
232
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
•
•
CPU
XGATE
“Master3”
Protects memory from undesired accesses coming from up to 3 bus masters
Eight memory protection descriptors
— each descriptor can cover the full global memory map (8 MBytes)
— each descriptor has a granularity of 8 Bytes
Data Access
Op-code Fetch
Data Access
Op-code Fetch
Data Access
shows a block diagram of the MPU module.
Features
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 4-1. Block Diagram
Access Validation
Access Validation
Access Validation
MPU Monitoring
MPU Monitoring
MPU Monitoring
MMC
Access Violation
Interrupt
1
Freescale Semiconductor
Registers
Status
MPU