C8051F019-GQ Silicon Laboratories Inc, C8051F019-GQ Datasheet - Page 111
![IC 8051 MCU 16K FLASH 48TQFP](/photos/12/38/123852/c8051f019-gq_sml.jpg)
C8051F019-GQ
Manufacturer Part Number
C8051F019-GQ
Description
IC 8051 MCU 16K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F018r
Specifications of C8051F019-GQ
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
4
Operating Supply Voltage
2.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
No. Of I/o's
16
Ram Memory Size
1.25KB
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1198
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F019-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F019-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
111
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
C8051F018
C8051F019
SPIF
R/W
Bit7
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is
not automatically cleared by hardware. It must be cleared by software.
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) to indicate a write to
the SPI data register was attempted while a data transfer was in progress. It is cleared by
software.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) when a master mode
collision is detected (NSS is low and MSTEN = 1). This bit is not automatically cleared by
hardware. It must be cleared by software.
This bit is set to logic 1 by hardware (and generates a SPI interrupt) when the receive
buffer still holds unread data from a previous transfer and the last bit of the current transfer
is shifted into the SPI shift register. This bit is not automatically cleared by hardware. It
must be cleared by software.
This bit is set to logic 1 by hardware while a master mode transfer is in progress. It is
cleared by hardware at the end of the transfer.
This bit is set to logic 1 whenever the NSS pin is low indicating it is enabled as a slave. It
is cleared to logic 0 when NSS is high (slave disabled).
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
SPIF: SPI Interrupt Flag.
MODF: Mode Fault Flag.
RXOVRN: Receive Overrun Flag.
TXBSY: Transmit Busy Flag.
SLVSEL: Slave Selected Flag.
MSTEN: Master Mode Enable.
SPIEN: SPI Enable.
WCOL
R/W
Bit6
MODF
R/W
Bit5
Figure 15.6. SPI0CN: SPI Control Register
RXOVRN
R/W
Bit4
Rev. 1.2
TXBSY
Bit3
R
SLVSEL
Bit2
R
MSTEN
R/W
Bit1
(bit addressable)
SPIEN
R/W
Bit0
SFR Address:
Reset Value
00000000
0xF8