C8051F019-GQ Silicon Laboratories Inc, C8051F019-GQ Datasheet - Page 121
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C8051F019-GQ
Manufacturer Part Number
C8051F019-GQ
Description
IC 8051 MCU 16K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F018r
Specifications of C8051F019-GQ
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
4
Operating Supply Voltage
2.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
No. Of I/o's
16
Ram Memory Size
1.25KB
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1198
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F019-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F019-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
17. TIMERS
Each MCU implements four counter/timers: three are 16-bit counter/timers compatible with those found in the
standard 8051, and one is a 16-bit timer for use with the ADC, SMBus, or for general purpose use. These can be
used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1
are nearly identical and have four primary modes of operation. Timer 2 offers additional capabilities not available
in Timers 0 and 1. Timer 3 is similar to Timer 2, but without the capture or Baud Rate Generator modes.
When functioning as a timer, the counter/timer registers are incremented on each clock tick. Clock ticks are derived
from the system clock divided by either one or twelve as specified by the Timer Clock Select bits (T2M-T0M) in
CKCON. The twelve-clocks-per-tick option provides compatibility with the older generation of the 8051 family.
Applications that require a faster timer can use the one-clock-per-tick option.
When functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected
input pin for T0, T1, or T2. Events with a frequency of up to one-fourth the system clock’s frequency can be
counted. The input signal need not be periodic, but it should be held at a given level for at least two full system
clock cycles to ensure the level is sampled.
17.1.
Timer 0 and Timer 1 are accessed and controlled through SFRs. Each counter/timer is implemented as a 16-bit
register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1).
Counter/Timer Control (TCON) register is used to enable Timer 0 and Timer 1 as well as indicate their status. Both
counter/timers operate in one of four primary modes selected by setting the Mode Select bits M1-M0 in the
Counter/Timer Mode (TMOD) register. Each timer can be configured independently. Following is a detailed
description of each operating mode.
17.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as a 13-bit counter/timer in Mode 0. The following describes the configuration and
operation of Timer 0. However, both timers operate identically and Timer 1 is configured in the same manner as
described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions TL0.4-
TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or ignored when
reading. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer
overflow flag TF0 (TCON.5) is set and an interrupt will occur if enabled.
The C/T0 bit (TMOD.2) selects the counter/timer’s clock source. Clearing C/T selects the system clock as the input
for the timer. When C/T0 is set to logic 1, high-to-low transitions at the selected input pin increment the timer
register. (Refer to Port I/O Section 13.1 for information on selecting and configuring external I/O pins.)
121
Timer 0 and Timer 1:
13-bit counter/timer
16-bit counter/timer
8-bit counter/timer with auto-reload
Two 8-bit counter/timers (Timer 0 only)
C8051F018
C8051F019
Timer 0 and Timer 1
Timer 2:
16-bit counter/timer with auto-reload
16-bit counter/timer with capture
Baud rate generator
Rev. 1.2
Timer 3:
16-bit timer with auto-reload
The