C8051F019-GQ Silicon Laboratories Inc, C8051F019-GQ Datasheet - Page 45
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C8051F019-GQ
Manufacturer Part Number
C8051F019-GQ
Description
IC 8051 MCU 16K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F018r
Specifications of C8051F019-GQ
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
4
Operating Supply Voltage
2.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
No. Of I/o's
16
Ram Memory Size
1.25KB
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1198
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F019-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F019-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
execute, and usually have a maximum system clock of 12MHz. By contrast, the CIP-51 core executes 70% of its
instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles.
With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. The CIP-51 has a total
of 109 instructions. The number of instructions versus the system clock cycles required to execute them is as
follows:
Programming and Debugging Support
A JTAG-based serial interface is provided for in-system programming of the Flash program memory and
communication with on-chip debug support circuitry. The reprogrammable Flash can also be read and changed a
single byte at a time by the application software using the MOVC and MOVX instructions. This feature allows
program memory to be used for non-volatile data storage as well as updating program code under software control.
The on-chip debug support circuitry facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints and watch points, starting, stopping and single stepping through program execution (including interrupt
service routines), examination of the program’s call stack, and reading/writing the contents of registers and memory.
This method of on-chip debugging is completely non-intrusive and non-invasive, requiring no RAM, Stack, timers,
or other on-chip resources.
The CIP-51 is supported by development tools from Silicon Laboratories and third party vendors. Silicon Labs
provides an integrated development environment (IDE) including editor, macro assembler, debugger and
programmer. The IDE’s debugger and programmer interface to the CIP-51 via its JTAG interface to provide fast
and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also
available.
8.1.
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set.
Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the
binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect
on PSW flags. However, instruction timing is different than that of the standard 8051.
8.1.1.
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles
varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle
timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as
there are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete
when the branch is not taken as opposed to when the branch is taken. Table 8.1 is the CIP-51 Instruction Set
Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction.
8.1.2.
The MOVX instruction is typically used to access external data memory. In the CIP-51, the MOVX instruction can
access the on-chip program memory space implemented as reprogrammable Flash memory using the control bits in
the PSCTL register (see Figure 9.1). This feature provides a mechanism for the CIP-51 to update program code and
use the program memory space for non-volatile data storage. MOVX is still used to read/write this external RAM
with the PSCTL register configured for accessing the external data memory space. Refer to Section 9 (Flash
Memory) for further details.
45
C8051F018
C8051F019
Clocks to Execute
INSTRUCTION SET
Instruction and CPU Timing
MOVX Instruction and Program Memory
Instructions
26
1
50
2
2/3
Rev. 1.2
5
14
3
3/4
7
3
4
4/5
1
2
5
1
8