C8051F019-GQ Silicon Laboratories Inc, C8051F019-GQ Datasheet - Page 142
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C8051F019-GQ
Manufacturer Part Number
C8051F019-GQ
Description
IC 8051 MCU 16K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F018r
Specifications of C8051F019-GQ
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
4
Operating Supply Voltage
2.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
No. Of I/o's
16
Ram Memory Size
1.25KB
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1198
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F019-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F019-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
18.2.
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of
the 16-bit counter/timer and PCA0L is the low byte (LSB).
PCA0H at the same time. By reading the PCA0L Register first, this allows the PCA0H value to be held (at the time
PCA0L was read) until the user reads the PCA0H Register. Reading PCA0H or PCA0L does not disturb the
counter operation. The CPS1 and CPS0 bits in the PCA0MD register select the timebase for the counter/timer as
shown in Table 18.2.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to
logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1
enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software. (Note: PCA0 interrupts must be
globally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit
(IE.7) and the EPCA0 bit in EIE1 to logic 1.) Clearing the CIDL bit in the PCA0MD register allows the PCA to
continue normal operation while the microcontroller core is in Idle mode.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
PCA Counter/Timer
CPS1
C
D
L
I
0
0
1
1
PCA0MD
00
01
10
11
C
P
S
1
C
CPS0
P
S
0
E
C
F
0
1
0
1
IDLE
Figure 18.7. PCA Counter/Timer Block Diagram
C
F
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided by 4)
C
R
Table 18.2. PCA Timebase Input Options
PCA0CN
C
C
F
4
C
C
F
3
C
C
F
2
C
C
F
1
C
C
F
0
Rev. 1.2
0
1
PCA0L
read or
write
Snapshot
Register
PCA0H
Reading PCA0L automatically latches the value of
PCA0L
To SFR Bus
To PCA Modules
Overflow
C8051F018
C8051F019
CF
To PCA Interrupt System
142