M30263F6AFP#U5A Renesas Electronics America, M30263F6AFP#U5A Datasheet - Page 88

• Manufacturer Part Number: M30263F6AFP#U5A
• Description: IC M16C/26A MCU FLASH 42-SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30263F6AFP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 33
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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R
M
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E
1
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J
Table 9.3.3.1. Settings of Interrupt Priority
6
0
9.3.1 I Flag
9.3.2 IR Bit
9.3.3 ILVL2 to ILVL0 Bits and IPL
ILVL2 to ILVL0 bits
2
C
9
0 .
B
2 /
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the
maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is
cleared to “0” (= interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 9.3.3.1 shows the settings of interrupt priority levels and Table 9.3.3.2 shows the interrupt priority
levels enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag is set to “1”
· IR bit is set to “1”
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
0
0
6
2
A
0
F
000
001
010
011
100
101
110
111
2
e
G
0 -
b
2
2
2
2
2
2
2
2
1 .
o r
2
0
, 5
u
0
p
2
0
(
Levels
M
0
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
7
1
6
C
Interrupt priority
page 69
2 /
6
, A
level
M
1
f o
6
C
3
2
2 /
9
6
, B
M
1
Priority
6
order
High
Low
C
2 /
6
) T
Table 9.3.3.2. Interrupt Priority Levels
000
001
010
011
100
101
110
111
IPL
2
2
2
2
2
2
2
2
Enabled by IPL
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
Enabled interrupt priority levels
9. Interrupt