HD64F3694FPJV Renesas Electronics America, HD64F3694FPJV Datasheet - Page 208

• Manufacturer Part Number: HD64F3694FPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3694FPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Timer W
12.5.7
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure
12.22 shows the timing of the IMFA to IMFD flag setting at input capture.
12.5.8
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag
is cleared. Figure 12.23 shows the status flag clearing timing.
Rev.5.00 Nov. 02, 2005 Page 178 of 418
REJ09B0028-0500
Timing of IMFA to IMFD Setting at Input Capture
Timing of Status Flag Clearing
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture
Input capture
signal
TCNT
GRA to GRD
IMFA to IMFD
IRRTW
Address
Write signal
IMFA to IMFD
IRRTW
Figure 12.23 Timing of Status Flag Clearing by CPU
N
TSRW write cycle
TSRW address
T1
T2
N