HD64F3694FPJV Renesas Electronics America, HD64F3694FPJV Datasheet - Page 445

MCU 3/5V 32K J-TEMP PB-FREE 64-L

HD64F3694FPJV

Manufacturer Part Number
HD64F3694FPJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3694FPJV

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
A
A/D converter ......................................... 265
Address break ........................................... 63
Addressing modes..................................... 34
C
Clock pulse generators.............................. 69
Condition field.......................................... 33
Condition-code register (CCR)................. 19
CPU .......................................................... 13
E
EEPROM................................................ 277
Sample-and-hold circuit...................... 272
Scan mode........................................... 271
Single mode ........................................ 271
Absolute address................................... 36
Immediate ............................................. 36
Memory indirect ................................... 37
Program-counter relative ...................... 36
Register direct....................................... 35
Register indirect.................................... 35
Register indirect with displacement...... 35
Register indirect with post-increment... 35
Register indirect with pre-decrement.... 36
Prescaler S ............................................ 73
Prescaler W........................................... 73
Subclock generator ............................... 72
System clock generator......................... 70
Acknowledge ...................................... 281
Acknowledge polling.......................... 284
Byte write ........................................... 283
Current address read ........................... 285
EEPROM interface ............................. 280
Page write ........................................... 283
Index
Effective address....................................... 38
Effective address extension....................... 33
Exception handling ................................... 49
F
Flash memory ........................................... 87
G
General registers ....................................... 18
I
I/O ports .................................................. 109
Random address read .......................... 286
Sequential read.................................... 286
Slave address reference register
(ESAR)................................................ 281
Slave addressing.................................. 281
Start condition..................................... 280
Stop condition ..................................... 281
Reset exception handling ...................... 56
Trap instruction..................................... 49
Boot mode............................................. 93
Boot program ........................................ 93
Erase/erase-verify ............................... 100
Erasing units ......................................... 87
Error protection................................... 103
Hardware protection............................ 103
Power-down state................................ 104
Program/program-verify ....................... 98
Programmer mode............................... 104
Programming units................................ 87
Programming/erasing in user
program mode ....................................... 96
Software protection............................. 103
Rev.5.00 Nov. 02, 2005 Page 415 of 418
REJ09B0028-0500

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