HD64F3694FPJV Renesas Electronics America, HD64F3694FPJV Datasheet - Page 301
![MCU 3/5V 32K J-TEMP PB-FREE 64-L](/photos/28/61/286107/64-lqfp__plqp0064kc-a_sml.jpg)
HD64F3694FPJV
Manufacturer Part Number
HD64F3694FPJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3694GFYV.pdf
(452 pages)
Specifications of HD64F3694FPJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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16.4
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes; single mode and scan mode. When changing the operating mode or analog input
channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The
ADST bit can be set at the same time as the operating mode or analog input channel is changed.
16.4.1
In single mode, A/D conversion is performed once for the analog input of the specified single
channel as follows:
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to software or
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST
16.4.2
In scan mode, A/D conversion is performed sequentially for the analog input of the specified
channels (four channels maximum) as follows:
1. When the ADST bit in ADCSR is set to 1 by software or external trigger input, A/D
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1.
4. The ADST bit is not automatically cleared to 0. Steps [2] and [3] are repeated as long as the
external trigger input.
register of the channel.
this time, an ADI interrupt request is generated.
bit is automatically cleared to 0 and the A/D converter enters the wait state.
conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1).
the A/D data register corresponding to each channel.
If the ADIE bit is set to 1 at this time, an ADI interrupt requested is generated. A/D conversion
starts again on the first channel in the group.
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
Operation
Single Mode
Scan Mode
Rev.5.00 Nov. 02, 2005 Page 271 of 418
Section 16 A/D Converter
REJ09B0028-0500
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