HD64F3694FPJV Renesas Electronics America, HD64F3694FPJV Datasheet - Page 70

MCU 3/5V 32K J-TEMP PB-FREE 64-L

HD64F3694FPJV

Manufacturer Part Number
HD64F3694FPJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3694FPJV

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-LQFP
For Use With
R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 2 CPU
2.6
CPU operation is synchronized by a system clock ( ) or a subclock (
edge of or
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Rev.5.00 Nov. 02, 2005 Page 40 of 418
REJ09B0028-0500
Basic Bus Cycle
Access to On-Chip Memory (RAM, ROM)
SUB
to the next rising edge is called one state. A bus cycle consists of two states or
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
or
SUB
Figure 2.9 On-Chip Memory Access Cycle
T
1
state
Bus cycle
Address
Write data
Read data
T
2
state
SUB
). The period from a rising

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