MC908AZ60AVFUER Freescale Semiconductor, MC908AZ60AVFUER Datasheet - Page 165

• Manufacturer Part Number: MC908AZ60AVFUER
• Description: IC MCU 64K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the COP prescaler.
15.3.7 COPD
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. (See
Chapter 11 Configuration Register
15.3.8 COPL
The COPL signal reflects the state of the COP rate select bit. (COPL) in the configuration register. (See
Chapter 11 Configuration Register
15.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
15.5 Interrupts
The COP does not generate CPU interrupt requests.
15.6 Monitor Mode
The COP is disabled in monitor mode when V
15.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
15.7.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the
COP counter in a CPU interrupt routine.
Freescale Semiconductor
Address:
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
$FFFF
Bit 7
Figure 15-2. COP Control Register (COPCTL)
6
(CONFIG-1)).
(CONFIG-1)).
5
Hi
Low Byte of Reset Vector
is present on the IRQ pin or on the RST pin.
Unaffected by Reset
Clear COP Counter
4
3
2
1
COP Control Register
Bit 0
165