MC908AZ60AVFUER Freescale Semiconductor, MC908AZ60AVFUER Datasheet - Page 194

• Manufacturer Part Number: MC908AZ60AVFUER
• Description: IC MCU 64K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Communications Interface (SCI)
PEN — Parity Enable Bit
PTY — Parity Bit
18.8.2 SCI Control Register 2
SCI control register 2:
194
This read/write bit enables the SCI parity function. (See
inserts a parity bit in the most significant bit position. (See
This read/write bit determines whether the SCI generates and checks for odd parity or even parity.
(See
•
•
•
•
•
0 = Idle character bit count begins after start bit
1 = Parity function enabled
0 = Parity function disabled
1 = Odd parity
0 = Even parity
Enables the following CPU interrupt requests:
–
–
–
–
Enables the transmitter
Enables the receiver
Enables SCI wakeup
Transmits SCI break characters
Table
Enables the SCTE bit to generate transmitter CPU interrupt requests
Enables the TC bit to generate transmitter CPU interrupt requests
Enables the SCRF bit to generate receiver CPU interrupt requests
Enables the IDLE bit to generate receiver CPU interrupt requests
18-8). Reset clears the PTY bit.
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
M
0
1
0
0
1
1
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Control Bits
PEN:PTY
0X
0X
10
11
10
11
Table 18-8. Character Format Selection
Start
Bits
1
1
1
1
1
1
Data
Bits
8
9
7
7
8
8
NOTE
Character Format
Parity
None
None
Even
Even
Table
Odd
Odd
Table
18-8). When enabled, the parity function
18-7). Reset clears the PEN bit.
Stop
Bits
1
1
1
1
1
1
Character
Length
10 Bits
11 Bits
10 Bits
10 Bits
11 Bits
11 Bits
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