HD64F2218TF24 Renesas Electronics America, HD64F2218TF24 Datasheet - Page 438

• Manufacturer Part Number: HD64F2218TF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218TF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Rev.7.00 Dec. 24, 2008 Page 382 of 698
REJ09B0074-0700
Bit
3
2
Bit Name Initial Value R/W
PER
TEND
0
1
R/(W)*
R
1
Description
Parity Error
Indicates that a parity error occurred during reception
using parity addition in asynchronous mode, causing
abnormal termination.
[Setting condition]
•
[Clearing condition]
•
Transmit End
This bit is set to 1 when no error signal has been sent
back from the receiving end and the next transmit data is
ready to be transferred to TDR.
[Setting conditions]
•
•
The timing of bit setting differs according to the register
setting as follows:
When GM = 0 and BLK = 0, 12.5 etu after transmission
starts
When GM = 0 and BLK = 1, 11.5 etu after transmission
starts
When GM = 1 and BLK = 0, 11.0 etu after transmission
starts
When GM = 1 and BLK = 1, 11.0 etu after transmission
starts
[Clearing conditions]
•
•
When a parity error is detected during reception
If a parity error occurs, the receive data is transferred
to RDR but the RDRF flag is not set. Also, subsequent
serial reception cannot be continued while the PER
flag is set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
When 0 is written to PER after reading PER = 1*
The PER flag is not affected and retains its previous
state when the RE bit in SCR is cleared to 0.
When the TE bit in SCR is 0 and the ERS bit is also 0
When the ERS bit is 0 and the TDRE bit is 1 after the
specified interval following transmission of 1-byte data.
When 0 is written to TDRE after reading TDRE = 1
When the DMAC is activated by a TXI interrupt and
transfers transmission data to TDR
2