DF36034GFPJV Renesas Electronics America, DF36034GFPJV Datasheet - Page 212
![MCU 3/5V 32K J TEMP PB-FREE 64LQ](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36034GFPJV
Manufacturer Part Number
DF36034GFPJV
Description
MCU 3/5V 32K J TEMP PB-FREE 64LQ
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of DF36034GFPJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 12 Timer Z
12.3.8
General Registers A, B, C, and D (GRA, GRB, GRC, and GRD)
GR are 16-bit registers. Timer Z has eight general registers (GR), four for each channel. The GR
registers are dual function 16-bit readable/writable registers, functioning as either output compare
or input capture registers. Functions can be switched by TIORA and TIORC.
The values in GR and TCNT are constantly compared with each other when the GR registers are
used as output compare registers. When the both values match, the IMFA to IMFD flags in TSR
are set to 1. Compare match outputs can be selected by TIORA and TIORC.
When the GR registers are used as input capture registers, the TCNT value is stored after detecting
external signals. At this point, IMFA to IMFD flags in the corresponding TSR are set to 1.
Detection edges for input capture signals can be selected by TIORA and TIORC.
When PWM mode, complementary PWM mode, or reset synchronous PWM mode is selected, the
values in TIORA and TIORC are ignored. Upon reset, the GR registers are set as output compare
registers (no output) and initialized to H'FFFF. The GR registers cannot be accessed in 8-bit units;
they must always be accessed as a 16-bit unit.
Rev. 4.00 Mar. 15, 2006 Page 178 of 556
REJ09B0026-0400
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