DF36034GFPJV Renesas Electronics America, DF36034GFPJV Datasheet - Page 255
![MCU 3/5V 32K J TEMP PB-FREE 64LQ](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36034GFPJV
Manufacturer Part Number
DF36034GFPJV
Description
MCU 3/5V 32K J TEMP PB-FREE 64LQ
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of DF36034GFPJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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12.4.8
Buffer operation differs depending on whether GR has been designated for an input capture
register or an output compare register, or in reset synchronous PWM mode or complementary
PWM mode.
Table 12.8 shows the register combinations used in buffer operation.
Table 12.8 Register Combinations in Buffer Operation
When GR is Output Compare Register: When a compare match occurs, the value in the buffer
register of the corresponding channel is transferred to the general register.
This operation is illustrated in figure 12.35.
When GR is Input Capture Register: When an input capture occurs, the value in TCNT is
transferred to the general register and the value previously stored in the general register is
transferred to the buffer register.
This operation is illustrated in figure 12.36.
General Register
GRA
GRB
Buffer register
Buffer register
Buffer Operation
Input capture
signal
Figure 12.35 Compare Match Buffer Operation
Figure 12.36 Input Capture Buffer Operation
Buffer Register
GRC
GRD
Compare match signal
General
register
General
register
Comparator
Rev. 4.00 Mar. 15, 2006 Page 221 of 556
Section 12 Timer Z
TCNT
REJ09B0026-0400
TCNT
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